In recent years, the demand for low-power and low-voltage memory has increased as portable and handheld devices such as PDAs, cellular phones, and notebook computers have become more popular. With such features, i.e., low power and low voltage memory, longer battery life in these popular portable devices is possible.
An issue when designing low-power and low-voltage memory is accounting for the self-refresh current. The self-refresh current (IDD6) is a current used by devices in standby modes. As such, the self-refresh current is an important parameter in the low-power and low-voltage memory design.
The self-refresh current can be expressed as follows:
                    IDD6        =                                            Iarray              +              Iperi                        Tref                    +                      I            DC                                              (        1        )            where Iarray, Iperi, IDC, and Tref denote an array current, a peripheral current, a DC current, and a refresh period, respectively. The DC current IDC is generally small, and the array current Iarray is the largest factor in the self-refresh current IDD6. Tref is a fixed refresh period and is determined by the refresh characteristics of the cells. Since cells generally refresh most frequently at a higher temperature, the refresh period Tref is determined using high temperature conditions.
Referring to FIGS. 1A, 1B, 2A, and 2B, conventional analog and/or digital designs have attempted to minimize/address power consumption by the self-refresh current IDD6. The oscillator 100 generates a base frequency, for example, 0.5× and the frequency divider generates additional refresh periods, i.e., 1×, 2× and 4× refresh periods, using the base frequency. A conventional oscillator circuit and the timing diagram of the oscillator is a current analog solution, as shown in FIGS. 1A and 1B. Such a prior art oscillator has a current source 110, a capacitor 120, a comparator 130, and a reset circuit 140. The reset circuit 140 initializes node l 150 to ground. The current source 110 provides a constant current i to node l 150, and the value at node l 150 increases linearly according to the capacitance C 120 and current i provided by the current source 110. When the voltage at the node l 150 reaches the level of the reference voltage Vref 170, the output 180 of the comparator 130 is switched to ‘H’, and node l 150 is reset to ground for the next operation. The oscillator period Tosc (see FIG. 1B) is determined by the capacitor C 120, the current i from the current source 110, and the reference voltage Vref 170.
Referring to FIG. 2A, a solution using digital logic to generate various refresh periods is also known. The oscillator 200 generates a base frequency, for example, 0.5× and the frequency divider 290 generates additional refresh periods, i.e., 1×, 2× and 4× refresh periods 292, 294, 296, using the base frequency. As shown in the table (see FIG. 2B), intermediate refresh periods, i.e., 1.5×, 2.5×, and 3.5×, are generated by combinational logic 220. Using the refresh periods generated by the oscillator 200, the frequency divider 290, and the combinational logic 220, one refresh period can be selected, i.e., TD<0:7>. The refresh period can be selected by the temperature information device (not shown), which provides the temperature information from a Temperature Compensated Self Refresh (TCSR) mode or an on-chip thermometer.
However, using only digital logic requires a large amount of space and is very complex. A frequency divider and combinational logic further increase the complexity in order to determine the additional refresh periods.
A simple method to vary refresh periods of an oscillator using minimal space as compared to a purely digital solution is desirable.